MicrosoftEmployer profile
Senior Design Verification Engineer
Location not specified · Experience not specified
Experience- Experience not specified
Salary- Not disclosed
Location- Location not specified
- Work mode
- Not specified
- Job type
- Full-time
Apply by- Closing date not listed
- Posted
- 11 Nov 32
About this role
Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world. Microsoft’s Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high-performance Azure cloud servers, clients, and augmented reality.We are looking for a design verification engineers to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) Silicon team. The candidate must be a highly motivated self-starter who will thrive in this cutting-edge technical environment.
Responsibilities
The AISoC silicon team is seeking a passionate, driven, and intellectually curious computer/electrical engineer to deliver premium-quality designs once considered impossible. We are responsible for delivering cutting-edge, custom IP and SoC designs that can perform complex and high-performance functions in an extremely efficient manner.
- Plan the verification of complex design IP/SoC interacting with the architecture and design engineers to identify verification test scenarios.
- Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools
- Develop tests using UVM or C/C++
- Analyse and debug test failures with designers to deliver functionally correct design.
- Identify and write functional coverage for stimulus and corner cases.
- Close coverage to plug verification holes and meet tape out requirements.
- 7 or more years of experience in design verification with a proven track record of delivering complex CPU or SoC IP’s
- In depth knowledge of verification principles, testbenches, stimulus generation, and UVM or C++ based test environments.
- Solid understanding of computer architecture
- Substantial background in debugging RTL (Verilog) designs as well as simulation and/or emulation environments
- Scripting language such as Python or Perl
- Hands on experience in Formal property verification
- knowledge in high-speed protocols like DDR, PCIe, Ethernet
- Processor based testbenches and emulation
Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.